1. Field of the Invention
The present invention relates to a semiconductor integrated circuit having transistors formed on a semiconductor substrate, an insulation substrate or a glass substrate and, more particularly, to a semiconductor integrated circuit capable of being laid out in a small-width region and a circuit layout designing method enabling such layout.
2. Description of the Related Art
For display devices and sensors, a method has generally been used in which peripheral circuits for driving a group of transistors (active matrix) for controlling display elements or sensor elements are mounted around a display region or a sensing region or formed on the same substrate as that for the active matrix (see, for example, patent documents 1 and 2 shown below. To increase the display region or the sensing region, the peripheral circuit is placed in straight narrow regions around the display region or the sensing region. A small-width peripheral circuit layout is made in such narrow regions, thus making it possible to provide a narrow-frame display device or sensor having an increased display or sensing region. Signal lines and power supply lines from external are connected by a flexible printed circuit (FPC) or the like to the peripheral circuits from a frame portion of the device. Therefore the external connection terminals of the peripheral circuits are concentrated on one side and the degree of freedom of layout is low. On the other hand, there is a need to increase the width of power supply lines in comparison with that of other signal lines for the purpose of limiting a voltage drop and power consumption when large currents flow through the power supply lines by concentration of currents flowing through the circuits in the device.
FIG. 2 shows a circuit for switching between power supply lines as an example of a circuit including three or more power supply lines. FIG. 32 shows an example of a possible case of layout of this circuit in a small-width region. In the switching circuit, a power supply line a34 is selectively connected to a line A32 or a line B33 through a gate signal φ. Since the circuit is constituted by two transistors 10 and 11, gate electrodes 30 and 31 each having a gate length Lg and a gate width Wg are aligned in one direction to make a small-width layout. That is, the power supply lines A32 and B32 having a length Wg and a width W are placed by the side of the gate electrodes 30 and 31 longitudinally aligned and the power supply line a34 having a length 2Wg and a width W is placed so as to face the gate electrodes 30 and 31. The power supply lines are each formed by a first metal layer and are electrically connected to active regions in the bodies of the transistors 10 and 11 through contacts (not shown). The layout width in this layout is the sum of the width of one gate and the width of two power supply lines (Lg+2W), which is small. For ease of explanation, the spacing between the gate electrodes and the first metal layer electrodes is assumed to be zero. The layout area is roughly expressed as (Lg+2W)×2Wg.
FIG. 33 shows an example of an ordinary possible layout in a case where the power supply lines A32 and B33 are connected from an upper side of a layout to external points and the power supply line a34 is wired in the layout. As wiring for internal connection, the power supply line a34 is extended downward as viewed in the figure so as not to increase the layout width. Similarly, as wiring for connection to external points, the power supply lines A32 and B33 are extended upward as viewed in the figure. However, the layout width is necessarily increased by an amount corresponding to the power supply line width W since the lines A32 and B33 are extended so as not to overlap each other. The layout area is thereby increased to (Lg+3W)×2Wg.
FIG. 34 shows an example of an arrangement in which the gate 30 is formed in such a manner that it is divided into sections and the sections are placed parallel to each other. The layout area of the gate 30 is thereby reduced. If the area of the gate electrode is not reduced by the parallel placement, the length of the gate region 30 is expressed as (Lg×Wg)/(Lg+W) since the gate area Lg×Wg of the gate region 30 of the transistor 10 is equal to that of the transistor 11. The layout area not including the wiring extensions in the arrangement shown in FIG. 34 is the product of the width (Lg+3W) and the length (Wg+(Lg×Wg)/(Lg+W)), i.e., (Lg+3W)×Wg×(2Lg+W)/(Lg+W). This area is always smaller than the area shown in FIG. 33 if W>0. In this layout, however, a change in layout cannot be made easily because the optimum parallel gate placement varies from transistor to transistor if the complexity of the circuit is increased.
(Patent Document 1)
Japanese Patent No. 2697728
(Patent Document 2)
Japanese Patent Laid-Open No. 10-133232
Circuit layouts such as those shown in FIGS. 32 to 34 are ordinarily adopted as layouts for placement in a small-width region. In such circuit layouts, however, the layout area is increased or the transistor-to-transistor layout is complicated and a change in layout cannot be easily made. Moreover, in a case where external input/output terminals are concentrated on one side so that the degree of freedom of layout is low, the layout width is increased by extended wiring.